It is preferable to use an interrupt in 8051 microcontrollers to lessen the frequency of the interface device’s status checks.

The term “interrupt” from electrical engineering refers to an occurrence that momentarily halts the main program, transfers control to a specific code area, executes a function relating to the event, and then restarts the main program where it had left off.

Types of Interrupts in 8051 Microcontroller

The 8051 microcontrollers can identify five distinct events that prompt the program to divert from its usual course of operation. The following five interrupt sources in the 8051 are:

• Timer 0 overflow interrupt- TF0
• Timer 1 overflow interrupt- TF1
• External hardware interrupt- INT0
• External hardware interrupt- INT1
• Serial communication interrupt- RI/TITimer and Its Modes.

External interrupts are produced by additional interfacing devices or switches that are externally connected to the microcontroller. The timer and serial interrupts are internally generated by the microcontroller. These external interruptions can be level- or edge-triggered. The interrupt service routine is carried out by the microcontroller when an interrupt happens, matching the memory location to the interrupt that enabled it. bandar slot

Interrupt Structure of 8051 Microcontroller

All interrupts are disabled by the command “RESET,” thus a software program is required to enable them all. If any or all of these five interrupts are enabled, the relevant interrupt flags are set, as depicted in the picture. The priority, which is carried out by the IP interrupt priority register, determines whether any of these interrupts are set or cleared by a bit in a specific function register that is interrupt-enabled (IE).

Interrupt Enable (IE) Register:

This register controls whether the interrupt is enabled or disabled. In order to enable interruptions, EA must be set to one in this bit-addressable register. This register’s corresponding https://media.javajazzfestival.com/ bit enables specific interrupts, including timer, external, and serial inputs. Bits corresponding to 1 and 0 in the IE register below enable and disable the interrupt, respectively.

Interrupt Priority Register (IP): 

By setting or clearing the corresponding bit in the Interrupt Priority (IP) register, the priority levels of the interruptions can also be changed. As a result, the low-priority interrupt can interrupt the high-priority interrupt, but another low-priority interrupt cannot. The high-priority interrupt is also uninterruptible. In the absence of a certain interrupt priority, the microcontroller executes in the following order: INT0, TF0, INT1, TF1, and SI.

TCON Register:

In addition to the previously mentioned two registers, the TCON register, https://civil.stamforduniversity.edu.bd/as depicted in the image, describes the external interrupt that will be sent to the 8051 microcontrollers. The two external interrupts, which may be edge or level triggered, are specified by this register by a set or cleared by the pertinent bits in it. It is an addressable register as well.