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What are the Interrupts of 8086?

by Sonali

An interrupt is a condition that arises during the working of a microprocessor. The microprocessor can execute or initiate interrupt services through a subroutine called Interrupt service routine. There are three interrupts of 8086:

Hardware interrupt

The external pin receives the request for this interrupt of the microprocessor. The pins NMI and INTR are the two pins with hardware interrupts.

Software interrupt

In order to execute this interrupt INT ‘n’ instruction is used. In this instruction the value of n can vary from 00H-FFH. Therefore, software interrupts are capable of invoking 256 interrupts at a time.

Error conditions

Despite of external and software interrupts sometimes due to special instructions also interrupts can be set in 8086 microprocessors. The INT 0 interrupt is set if there is some error in division.

Interrupt Vector Table (IVT):

  • The interrupt pointer is the connection between the interrupt type code and the process which is also assigned to service interrupt.
  • The four byte memory is assigned for each interrupt.
  • The NEW CS is the base address of the segment which has a higher address word. Hence, NEW CS is responsible for providing the new address from where the interrupt service routine starts.
  • The lower address word has the procedure offset which has NEW IP.
  • We can segregate the interrupt vector table into three groups such as Dedicated interrupts which are from (INT 0…..INT 4). The second is Reserved interrupts which is from (INT 5…..INT 31)and lastly Available interrupts (INT 32…..INT 225).

 Dedicated interrupts (INT 0…..INT 4)


  • During division an error occurs and hence invoking this interrupt. The error can arise in cases when the divisor is smaller or zero than the dividend.
  • This ISR is at location 00000H in the interrupt vector table.

INT 1 

  • Whenever the TF bit is set this interrupt is executed.
  • The ISR address for this interrupt is having memory location 00004H in the interrupt vector table.

INT 2 

  • The INT2 is a non maskable interrupt. It has an ISR address of 00008H in the interrupt vector table.

INT 3 

  • This interrupt can be active through instruction INT or INT 03H and it also causes breakpoints in the program. 
  • If the programs are very large then this interrupt helps in debugging it.
  • This interrupt has the ISR location of 0000CH in the interrupt vector table.

INT 4 

  • This interrupt is overflow interrupt.
  • When overflow bit is set then they are active. This interrupt is active after the execution of INTO instruction.
  • Then overflow bit is usually set after the execution of signed arithmetic operations.
  • This interrupt also has the ISR location of 00010H in the interrupt vector table.

 Reserved interrupts

There are also some interrupts which are not available for the users. Then they are kept for higher processors. They are from INT5-INT31.

Available interrupts 

  • They range from INT 32- INT225 and are software interrupts. Users can define these interrupts as well.
  • The INT n instructions can invoke these interrupts.
  • This interrupt also has the ISR location of nx4 in the interrupt vector table.

Hardware Interrupts:

These interrupts can be further classified into two categories

NMI (Non mask-able interrupt)

  • These are non-maskable interrupts  and highest priority interrupts. 
  • Then INT instruction is executed on receiving these interrupts.
  • This interrupt has the ISR location of 2×4= 00008H in the interrupt vector table.
  • In order to obtain the values of IP and CS it reads four locations from this address to execute the ISR.


  • This is a low priority interrupt and is maskable as well. We can then level trigger these interrupts.
  • Then this microprocessor generates two INTR pulses on receiving an interrupt on the INTR line. 
  • The CLI instruction masks this request by setting IF=0.
  • The STI instruction unmasks this request by setting IF=1.

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