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What is Minimum Mode Configuration of 8086?

by Sonali

The microprocessor 8086 minimum mode and maximum mode operation is decided by signal MN/MX’. When the signal MN/MX’ = 1 the 8086 minimum mode is active.

8086 microprocessor operates in 2 modes :

1. Minimum mode

  • It can be selected by setting the MN/MX pin to logic 1 and it acts like a single microprocessor .
  • In this mode, all the control signals are provided by the microprocessor chip itself.

  2. Maximum mode

  • This operation can be selected by setting the MN/MX pin to logic 0 and the microprocessor acts like a multiprocessor.
  • It provides the signals for implementing a multi core processor system environment and in this each processor executes its own program.
  • In this type of system environment, some system resources that are common to all processors are present.
  • They are known as global resources.
  • Co processor means there is a second processor in the system, but both of them cannot access the system bus at the same time.
  • One processor passes the control of the system bus to the other & then can also suspend its operation.
Minimum Mode Circuit


  • It is an 8-bit latch. 
  • Basically it is a buffered D flip flop.
  • This latch separates the multiplexed address received from the data bus by using control signal ALE. This ALE signal is an active high signal.
  • This ALE signal is connected to the strobe of the latch.
  • We need 3 latches here because the address is 20 bits.


  • 8286 is an 8-bit transceiver.
  • They are data amplifiers and act as bidirectional buffers.
  • This trans receivers separates the multiplexed address received from the address or data bus. 
  • Since the data bus is 16 bits we require 2 trans receivers.
  • This transceiver is connected to signals DT/R’ and DEN’. These signals are enabled using DEN signals.
  •  DT/R’ controls the direction of data on the control bus and it is also connected to T and DEN’.


  • It is a clock generator used to provide clocks.
  • There is Input/ output transfer from the bus when signal M/IO’= 1. Also, when the signal M/IO’ = 0 input/output operations are performed.
  • The read (RD’) and write (WR’) signals are used to differentiate whether a read bus cycle or write bus cycle is performing.
  • When signal WR’=0 it performs write operation and when RD’=0 the microprocessor 8086 performs read operation.
  • The signal DEN is also used with RD’. This signal enables the external devices so that they can put data on the bus.
  • All these control signals (M/IO’, RD’, WR’) are decoded using a 3:8 decoder. Ic 74138 is a 3:8 decoder.

INTR and INTA : 

  • These are interrupt signals of an 8086 microprocessor. Whenever there is an interrupt from external devices to 8086 INTR=1.
  • When the processor is ready to provide service to external devices then signal INTA’= 0.
  •  The other devices can make bus requests by sending signal HOLD.
  • The 8086 acknowledges them through HLDA signals in return.

Timing diagram of 8086 Minimum Mode:

Opcode fetch / Read Timing Diagram

The processor cannot get the control of the bus until the master does not set HLDA=0.

Write Memory Cycle

The timing diagram of 8086 minimum mode operation is explained below.

  • There are four t-states of the bus cycle for microprocessor 8086. 
  • These T-states are T1,T2,T3 and T4
  • During the T1 state the processor gives the address on the bus for 1 T-state.
  • In T2 state the processor changes the bus direction.
  • In T3 and T4 states the data is transferred.  
  • The wait signal is also generated between T3 and T4 states.

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