The main components of Phase Locked Loop are a phase detector with a voltage controlled oscillator. One of the input to VCO is from the phase detector. Similarly, one of the inputs of a phase detector is connected to the output of VCO. Because of which a loop is formed as seen in figure.
Block Diagram of Phase Locked Loop
The three basic elements of PLL are
Phase comparator / detector: It is within PLL and compares the phase of two signals. Then voltage is produced depending upon the phase difference of the signals.
Voltage controlled oscillator, VCO: The voltage-controlled oscillator produces the output of the loop which is a radio frequency signal. This frequency can be controlled.
Loop filter: It filters the output from the phase comparator. It clears off the component of the signal after comparing its phase with the VCO input and the reference. It maintains the stability of loop and also speed of lock.
Operation
The basic blocks of PLL are voltage- controlled oscillator, phase detector, and the loop filter.
In the basic PLL, the reference signal and the signal from the voltage- controlled oscillator are connected to the two input ports of the phase detector.
The signal obtained after filtering from the loop filter is provided as an input to the voltage controlled oscillator. As we have already seen, the input to the phase detector is from the VCO. An error voltage is produced when phases of signals from VCO and the input reference signals are compared. This results in a phase difference between the two signals.
This signal then passes through the LPF and removes all the high frequency elements present. Then input to the control terminal of VCO is this error signal. At first the PLL is out of loop and the frequency of VCO is pulled near to reference by the error voltage and the error cannot be reduced now. Hence, the loop is now locked.
A steady state voltage is produced when the PLL is locked. Then actual error can be minimized by an amplifier which is in between the detector and the VCO.
When the phase difference between the reference signal and VCO is not changing we find a steady error voltage. This implies both signals are not exactly the same.
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