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How to design a Synchronous counter?

by Sonali
  • Synchronous counter is designed to count the number of clock pulses.
  • This counter is clocked with the same clock signal and at the same time.
  • Synchronous counters can be formed using T or JK flip flops and are edge triggered.
  • The flip flops will change their present state only when the next clock pulse arrives.

Design Steps:

The basic design steps for these counters are discussed in detail.

  • First we find the number of flip flops required for the design of a synchronous counter.
  • The number of flip flops can be determined from 2^n  ≥ N.

Where: N →number of states and n →number of flip flops.

  • Next ew select the flip flop for the design.
  • Then we draw the state diagram of that counter.
  • With the help of an excitation table of flip flops we determine the excitation table of the counter.
  • At last we simplify the excitation table using K-map.

Design for Mod-N counter 

The design of the mod-N synchronous counter is done through following steps.

Step 1 : Find number of flip flops 

For the mod N counter we can find the number of flip flops from relation 

N  <= 2n

Let us consider N= 10. So,

For n =3, 10<=8,  which is not true. Hence again considering n= 4


This holds true.

Therefore the number of flip flops required is 4 for the Mod-10 counter.

Step 2 : Excitation table of Flip flops 

We chose a T flip flop for the design. Then the excitation table for T flip flop is as shown 

Excitation Table for T Flip Flop

Step 3 : State diagram andCircuit excitation table 

The mod-10 counter counts ten states from 0 to 9. This counter is also called the decade counter. We use four flip flops here. They are reset When QD QC QB QA = 1001.

State Diagram

Circuit excitation table 

Now QD QC QB QA are the present states of flip-flops and Q*D Q*C Q*B Q*A is the next counting state of these Flip flops.

When there is transition in the present of QD the value changes from 0 to 1 or vice versa. 

Step 4 : Simplify K-map for each FF input in terms of flip-flop outputs as the input variable 

K-map Simplification

Step 5 :Circuit diagram 

The negative edge trigger is used for toggle.

  • The clock pulse is synchronous to all flip flops.
  • Then the input to every flip flop is as per the equation of K map.
Mod-10 Counter using T Flip Flop

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