Jharkhand University of Technology, Jharkhand, Electrical & Electronics Engineering Semester 4, Digital Electronics And Logic Design Syllabus

DIGITAL ELECTRONICS AND LOGIC DESIGN

Module I: Binary Codes and Boolean algebra
Analog and Digital, Binary Number System. Addition, Subtraction, Multiplication,
Division of binary numbers, Subtraction using 2’s complement method. Binary codes:
weighted and non weighted codes, self complementary codes, BCD, Excess-3, Gray
codes, Alphanumeric codes, ASCII Codes. Boolean algebra: Boolean Laws and
Expression using Logic
Gates, Realization of different gates using Universal gates, DeMorgan’s Theorem,
Duality Theorems.

Module II: Boolean function minimization Techniques
Standard forms: SOP, POS, Simplification of Switching function & representation
(Maxterm & Minterm), Boolean expression & representation using logic gates,
Propagation delay in logic gate. Karnaugh map: K-map(up to 5 variables), mapping
and minimization of SOP and POS expression, Don’t care condition, conversion from
SOP to POS and POS to SOP form using K-map, Minimization of multiple output
circuits, Quine Mc-cluskey method minimization technique, prime implicant table,
Don’t care condition.
Module III: Combinational Circuits Design
Adder & Subtractor (Half and Full), Parallel Binary adder, BCD Adder, Binary
multipliers, Code Converters, parity bit generator, Comparators, Decoder, BCD to 7-
segment Decoder, Encoders, Priority Encoders, Multiplexers, De Multiplexers.
Module IV: Sequential Circuits Elements
Introduction to sequential circuit, Flip-flop & Timing Circuits: SR latch, Gated latch,
Tri state logic, Edge triggered flip-plop: - D, JK, T Flip-flop, flip-flop asynchronous
inputs ,characteristic table of Flip-flop, excitation table of Flip-flop, master slave JK
flip flop, inter conversion of Flip-flop. Study of timing parameters of flip-flop. Shift
registers: buffer register, controlled buffer register. Data transmission in shift resistor
SISO, SIPO, PISO, PIPO, Bidirectional shift register, universal shift registers.
Counter: Classification, Ripple or asynchronous counter, Effect of propagation delay
in ripple counters, up-down counter, Design of Mod-n counter, synchronous counter,
Ring counter, Johnson counter. Introduction to FSM. Design of synchronous FSM,
Algorithmic State Machines charts. Designing synchronous circuits like Pulse train
generator.

Module V: Logic Families and VLSI Design flow
Logic Families and Semiconductor Memories: TTL NAND gate, Specifications, Noise
margin, Propagation delay, fan-in, fan-out, TTL, ECL, CMOS families and their
interfacing, Memory elements, Concept of Programmable logic devices like FPGA,
Logic implementation using Programmable Devices VLSI Design flow: Design entry,
Schematic, FSM & HDL, different modeling styles in VHDL, Data types and objects,
Dataflow, Behavioral and Structural Modeling, Synthesis and Simulation VHDL
constructs and codes for combinational and sequential circuits
Text Books :
1. Kharate “Digital Electronics” OXFORD Publication
2. A. Anand Kumar ‘Fundamentals of Digital Circuits’. PHI Publications 2nd year UG courses Engg & Tech, Jharkhand university of Technology.
3. R.P. Jain-‘Modern Digital Electronics’ IIIrd Edition- Tata Mc Graw Hill, Publication
4. Douglas Perry, “VHDL”, Tata McGraw Hill, 4th edition, 2002.
5. Charles Roth, “Digital System Design using VHDL”, Tata McGraw Hill 2nd edition
6. Bhaskar VHDL BASED DESIGN ,PEARSON EDUCATION

Reference Books:
1. Rajkamal ‘Digital Systems Principals and Design’ Pearson Education
2. A.P. Malvino, D.P. Leach ‘Digital Principles & Applicatios’ -VIth Edition-TMH
publication.
3. M. Morris Mano ‘Digital Design’ (Third Edition). PHI Publications