Savitribai Phule Pune University, Maharashtra (SPPU), Electronics and Telecommunications Semester 3, Digital Circuits Syllabus

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Unit - 1 Digital Logic Families

1.1 Classification and Characteristics of digital Logic Families Speed power dissipation figure of merit fan in fan out current voltage noise immunity operating temperatures and power supply requirements.

1.2 TTL logic

1.3 Operation of TTL NAND gate active pull up wired AND open collector output unconnected inputs.

1.4 TriState logic. CMOS logic CMOS inverter NAND NOR gates unconnected inputs wired logic open drain output.

1.5 Interfacing CMOS and TTL Data sheet specifications.

Unit - 2 Combinational Logic Design

2.1 Introduction

2.2 Standard Representation for Logical Functions

2.3 KarnaughMap representation of logical functions

2.4 Minimization of Logical functions using KMap

2.5 Don’t Care Conditions

2.6 Combinational Logic Design examples

2.7 Quine McCluskey Minimization Technique

Unit - 3 Combinational Circuits

3.1 Adders and their use as Subtractor

3.2 The LookAhead Carry Adder

3.3 Arithmetic Logic Unit ALU

3.4 Comparators

3.5 Parity Generators Checkers

3.6 Multiplexers and their use in combinational logic designs

3.7 Multiplexer Trees

3.8 Demultiplexers and their use in combinational logic designs

3.9 Demultiplexer Tree

Unit - 4 Sequential Logic Design

4.1 1 Bit Memory Cell Clocked SR JK MS JK flip flop D and T flipflops

4.2 Use of preset and clear terminals hold and setup time and metastability.

4.3 Excitation Table for a flip flop Conversion of flip flops Typical data sheet specifications of Flip flop application of Flip flops.

4.4 Registers Shift registers Counters ring counters twisted ring counters ripple counters Modn counters updown counters synchronous counters lockout Clock Skew Clock jitter.

4.5 Sequence Generators.

Unit - 5 State Machines

5.1 Basic design steps State diagram State table State reduction State assignment

5.2 Mealy and Moore machines representation Implementation finite state machine implementation Sequence detector.

5.3 Introduction to Algorithmic state machines construction of ASM chart and realization for sequential circuits

Unit - 6 Programmable Logic Devices

6.1 Introduction

6.2 PROM

6.3 PLA

6.4 PAL

6.5 FPGA

6.6 CPLD

6.7 Semiconductor Memories

6.8 Designing combinational circuits using PLD’s

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Other Subjects of Semester-1
Data structures
Electrical circuits
Electronic circuits
Engineering mathematics - iii
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