Shivaji University, Maharashtra, Electronics and Communication engineering Semester 6, VLSI Design Syllabus

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Unit - 1 MOS Devices
1.1 Introduction to MOS technology
1.2 IV Characteristics of NMOS and PMOS
1.3 Transfer Characteristics of CMOS Inverter
1.4 Detailed Analysis of CMOS Inverter
1.5 Logic Realization using nMOS and CMOS circuits
1.6 Effect of parasitic elements.
Unit - 2 CMOS IC Fabrication and Layout
2.1 Basic CMOS Technology
Unit - 3 Introduction To VHDL
3.1 Introduction to VHDL
3.2 Elements of VHDL
3.3 Modeling Styles
3.4 Sequential and Concurrent statements
3.5 Design Flow
3.6 Data types and Data Objects in VHDL
3.7 Operators
3.8 Sequential statements
3.9 Comparison of various Hardware Description Languages
3.10 Test Benches
Unit - 4 Design using VHDL
4.1 Designing basic gates
4.2 Combinational circuit
4.3 Designing general purpose processor
4.4 Datapath
4.5 ALU
4.6 Encoder and Decoder
4.7 Adder and Subtractor
4.8 Multiplexer and Demultiplexer
4.9 Tristate drivers
4.10 PIPO
Unit - 5 Circuit Design Using CPLD & FPGA
5.1 Introduction
5.2 Study of architecture of CPLDs and FPGAs
5.3 Function block architecture
5.4 InputOutput Block and interconnect
5.5 Switch Matrix
5.6 FPGA fabric
5.7 Study of architecture of Xilinx 9500 series and Altera MAX 700 series CPLD
5.8 Study of architecture of Xilinx Spartan 4000 architecture
Unit - 6 Design for Testability
6.1 Fault Model
6.2 Need for testability
6.3 Path Sensitizing
6.4 Random Tests
6.5 BIST
6.6 Boundary Scan Test
6.7 Introduction to fault coverage
6.8 Testability
6.9 Stuck at Fault model
6.10 Boundary scan test
6.11 JTAG technology
6.12 TAP controller
6.13 Scan path
Download ECE Sem 6 syllabus pdf
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Other Subjects of Semester-2
Control systems
Operating systems
Digital signal processing
Antenna & wave propagation
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