This volume contains papers presented at The 2013 International Conference on Computer Design (CDES’13). Their inclusion in this publication does not necessarily constitute endorsements by editors or by the publisher.
Additional Info
  • Publisher: Laxmi Publications
  • Language: English
  • ISBN : 978-93-84872-00-7
  • Chapter 1

    Allocation of NBTI Aging Sensors for Circuit Failure Prediction Price 2.99  |  2.99 Rewards Points

    Negative bias temperature instability (NBTI) is a critical device reliability concern in nanometer-scale CMOS processes. We review the degradation effects of this phenomenon and present techniques to measure and combat NBTI aging. Such techniques involve the insertion of specialized aging sensors and their use in self-correcting dynamic reliability management systems. We propose a novel approach to optimize the allocation of such aging sensors to minimize overhead.

  • Chapter 2

    Implementation of a Fast Fourier Transform Processor in NULL Convention Logic Price 2.99  |  2.99 Rewards Points

    The Fast Fourier Transform (FFT) is a critical part in communication systems, because it can greatly reduce the computation requirement for signal processing. This paper presents the design of a FFT processor using NULL Convention Logic (NCL), which has been shown to have power consumption advantages over its synchronous counterpart. Performance metrics for the NCL FFT processor are obtained from Cadence simulation, and compared to an equivalent synchronous implementation.

  • Chapter 3

    Network-Based System for Face Recognition on Mobile Wireless Devices Price 2.99  |  2.99 Rewards Points

    This paper describes new internet-based face recognition system to be used in portable devices. In contrast to existing systems, which run computationally intensive facerecognition tasks at a mobile terminal shortening its battery lifetime, the proposed system uses mobile device only for image capturing and user-interface. All complex image processing tasks are performed by a remote high-powered network server to achieve robust and real time face recognition. The system is implemented in software and tested on Android-based Sony Tablet-S wireless terminal. According to measurements, it provides face recognition in images of 240x320 pixels in size at 10f/sec rate with very high accuracy. The paper discusses the proposed client-server architecture and the results of its experimental evaluation.

  • Chapter 4

    A Fault Injection Environment for the Evaluation of a Soft Error Detection Technique based on Time Redundancy Price 2.99  |  2.99 Rewards Points

    This paper presents a Verilog test simulation environment designed to inject random transient faults on a 32-bit microprocessor. The purpose of the test environment is to study a hardware-assisted soft error detection technique based on time redundancy. The soft error detection method compares the states of the microprocessor of two independent executions of the same program. The simulation environment takes advantage of the redundant execution and divides the process in two phases. The first phase operates during the first execution of the program to determine the number of cycles that are required to complete the task when no faults are present. The second phase is performed during the second execution of the program to inject a soft error in the microprocessor. The hardware assistance saves the microprocessor states as the program is executing the first time and detects the soft error as they occur during the second execution.

  • Chapter 5

    A Comparative Analysis of Parallel Prefix Adders Price 2.99  |  2.99 Rewards Points

    All modern processors, including general purpose microprocessors, digital signal processors and GPUs contain an Arithmetic Logic Unit (ALU). The computing efficiency of modern processors mainly depends of the efficiency of the ALU. An adder is the basic building block for an ALU which performs arithmetic as well as logic operations. This paper investigates the performance of six different parallel prefix adders implemented using four different TSMC technology nodes. The parallel prefix adders investigated in
    this paper are: Kogge Stone Adder, Brent Kung Adder, Han Carlson Adder, Sklansky Adder, Lander Fischer Adder, and Knowles Adder. The performance metrics considered for the analysis of the adders are: power, delay and area. Simulation studies are carried out for 16, 32 and 64 bit input data width.

  • Chapter 6

    A Short Survey on User-aware Power Management Price 2.99  |  2.99 Rewards Points

    This paper briefly surveys user aware power management. In the past, most power saving techniques have been focused on power and performance. However, recently,
    there are some power management techniques that concentrate on user satisfaction rather than performance itself. After reading this paper, power management researchers are
    expected to collaborate with consumer researchers as well as HCI(Human Computer Interface) researchers.

  • Chapter 7

    Performance Tradeoff Spectrum of Integer and Floating Point Applications Kernels on Various GPUs Price 2.99  |  2.99 Rewards Points

    Floating point precision and performance and the ratio of floating point units to integer processing elements on a graphics processing unit accelerator all continue to present complex tradeoffs for optimising core utilisation on modern devices. We investigate various hybrid CPU and GPU combinations using a range of different GPU models occupying different points in this tradeoff space. We analyse some performance data for a range of numerical simulation kernels and discuss their use as benchmark problems for characterising such devices.

  • Chapter 8

    Performance Measures of an Implementation of a Parallel Compiler Price 2.99  |  2.99 Rewards Points

    Parallel programming is prevalent in every field mainly to speed up computation. Advancements in multiprocessor technology fuel this trend toward parallel programming. However, modern compilers are still largely single threaded and do not take advantage of the machine resources available to them. A good deal of research has been reported on compilers that add parallel constructs to the programs they are compiling, enabling programs to exploit parallelism at run time. Auto parallelization of loops by a compiler is one such example. Parallelizing the compilation process itself has received less attention.

  • Chapter 9

    SDD Selective De-Duplication with Index by File Size for Primary File Servers Price 2.99  |  2.99 Rewards Points

    We propose a method, called SDD, for improving performance of file level de-duplication for primary file servers. The processing time of the deduplication is increasing because more and more files are being stored in the servers, therefore the de-duplication process cannot finish during assigned time. According to previous studies, large files stored in the servers are dominant in terms of the storage space, while rather small files are dominant in terms of file count. SDD sets a file size threshold to narrow down target files. We develop and evaluate a prototype system using SDD, which increases the throughput of the de-duplication processes.

  • Chapter 10

    Iterative Synthesis Techniques for Multiple-Valued Logic Functions A Review and Comparison Price 2.99  |  2.99 Rewards Points

    A number of heuristics for near optimal functional synthesis of Multi-Valued Logic (MVL) have been reported in the literature. Among the well-known heuristics is the Direct Cover algorithm (DCA). We have introduced a number of improved versions of the DCA. These include the Weighted Direct Cover (WDC), the Ordered Direct Cover (ODC), and the Fuzzy Direct Cover (FDC). In this paper, we review and compare the performance of those heuristic iterative techniques using two set of benchmarks. The first consists of
    50000 randomly generated 2-variable 4-valued functions and the second consists of 50000 2-variable 5-valued functions. The average number of product terms required to synthesize a given MVL function is used as the criterion for comparison. The results obtained show that the modified iterative synthesis heuristics outperformed the DCA and that among the modified techniques the FDC produces the best results.

  • Chapter 11

    FPGA-based Hexapod Robot Spider Price 2.99  |  2.99 Rewards Points

    By Yuhua Li and Huimin Ma

  • Chapter 12

    3D Lattice Monte Carlo Simulations on FPGAs Price 2.99  |  2.99 Rewards Points

    Field Programmable Gate Arrays (FPGAs) offer significant performance advantages over general purpose compute architectures for certain scientific problems, including lattice-based Monte Carlo simulations of complex systems models. We report on a custom logic design for the 3D-lattice Ising model that keeps the entire system state in on-chip memory to achieve very high throughput rates. The pipelined architecture, which is implemented in Verilog, is able to process an entire row of cells per clock cycle. When processing a system of 2563 spins on a Xilinx Virtex-7 device, about 3000 full system sweeps can be performed per second. We discuss implementation issues and solutions that apply in similar ways to a variety of nearest neighbour, lattice-based Monte Carlo simulations, as well as the performance of the Ising model implementation on two FPGA architectures.

  • Chapter 13

    Redundancy Reconfigurability Recoverability Price 2.99  |  2.99 Rewards Points

    An approach to consider computers and connected computer systems using structural, time and information redundancies is proposed. An application of redundancy for reconfigurability and recoverability of computer and connected computer systems is discussed, gaining performance, reliability and power-saving in operation. A paradigm of recoverability is introduced and, if followed, shifts connected computer systems toward real-time applications. Use of redundancy for connected computers is analysed in terms of recoverability, where two supportive algorithms of forward and backward tracing are proposed and explained. As an example, growth of mission reliability is formulated.

About the Author Phone: 617-989-4142 Campus Address: 145 Dobbs Hall view complete profile

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Ashu M. G. Solo is an independent interdisciplinary researcher and developer, electrical engineer, computer engineer, intelligent systems engineer, political and public policy engineer, mathematician, political writer, public policy analyst, political operative, entrepreneur, former infantry platoon commander understudy, and progressive activist. Solo has over 500 research and political commentary publications. view complete profile

Fernando G. Tinetti's most popular book is Bioinformatics and Computational Biology. view complete profile

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