The post What is Digital to Analog Converter? appeared first on Goseeko blog.

]]>This DAC uses binary weighted resistors to produce analog output equivalent to the binary input. The binary input is provided to the inverting adder circuit. Below figure represents the weighted resistor DAC. We can represent the binary number in the form of bits b0, b1, b2. The bit b0 is the least significant bit. The bit b1 is the most significant bit. The switches present will jump to ground when the input is equal to zero. When the input is 1 the switches will switch to position -VR which is the negative reference voltage.

The circuit consists of an Op-Amp which is an inverting op-amp as input is provided through the negative terminal. As we know from the virtual ground concept, the value of voltage at inverting and no-invertig end of the op-amp will be the same. Hence, the value of voltage at the input terminal node will be equal to 0V.

The value of current at each node can be determined by writing the nodal equations.

We have a 3-bit binary weighted resistor DAC. As there are only three input bits b0-b2. Then the number of possible outputs can be from 000 to 111 for a particular reference voltage VR.

Now for N-bit binary weighted resistor DAC the general form of output voltage can be

This R-2R ladder DAC consists of R-2R ladder structure as shown below. Then the DAC produces analog output which is equal to the binary input. The ladder network then produces output with an inverting adder circuit in it. The figure below explains the circuit of R-2R ladder DAC.

Similar to Weighted Resistor DAC this circuit also has b0 as the least significant bit and b2 as the most significant bit. When the input bits are equal to 0 the digital switches jump to ground. When the input bits are 1 the switches jump to negative reference value -VR.

We can also easily find out the output voltage equation for this DAC for individual binary inputs. But it is very difficult to get the generalized output voltage equation in this case.

The reason why we prefer R-2R Ladder DAC over Weighted Resistor are

- The design of this type of DAC is easy as only R and 2R resistors are present.
- We can also include more R-2R combinations depending upon the required number of bits.

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]]>The post <strong>What is the CB Hybrid Model?</strong> appeared first on Goseeko blog.

]]>The hybrid two port model is shown below.

V_{i} = h_{11}I_{i} + h_{12}V_{o}

I_{o} = h_{21}I_{i} + h_{22}V_{o}

h_{11} = h_{i} = V_{i}/I_{o} for V_{o} =0 [Input resistance]

Reverse voltage gain

h_{12} = h_{r} = V_{i}/V_{o} for I_{i} =0

Then Forward current gain

h_{21} = h_{f} = I_{o}/I_{i} for V_{o} =0

Hence,

h_{22} = h_{o} = I_{o}/V_{o} for I_{i} =0 [output admittance]

The hybrid equivalent model is shown below

The transistor model has three terminals with two ports.

Input resistance = h_{i}

Output conductance= h_{o}

The reverse transfer voltage

h_{r}= V_{i}/V_{o}

h_{f}= I_{o}/I_{i} = forward transfer current ratio

The simplified model is shown below

Finding **current gain A _{i}**

Applying KCL at the output of above circuit

I_{o} =I + h_{f} I_{b} = V_{o} h_{o} + h_{f} I_{b}

V_{o} = -I_{o} R_{L}

Then

I_{o} = -I_{o} R_{L} h_{o} + h_{f} I_{b}

I_{o} (1 + R_{L} h_{o}) = h_{f} I_{b}

A_{i} = I_{o}/ I_{b} = h_{f}/(1 + R_{L} h_{o})

Finding **Voltage Gain A _{V}**

Applying KVL at input of the above h-model

V_{i} = h_{i} I_{b} + h_{r} V_{o}

But I_{b} = (1 + h_{o} R_{L})/h_{f}

I_{o} = – V_{o}/R_{L}

Substituting in above equation and solving for V_{o}/V_{i} we get

A_{v} = – h_{f} RL/h_{i} + (h_{i} h_{o}– h_{f} h_{r}) R_{L}

Finding **Input Impedance Z**_{i}

V_{i} = h_{i} I_{b} + h_{r} V_{o}

Then

I_{o} = – V_{o}/R_{L}

A_{i} = I_{o}/ I_{b}

Since

V_{i} = h_{i} I_{b} – h_{r}R_{L}A_{i}I_{b}

Hence the input impedance is

Z_{i} = V_{i}/I_{b} = h_{i} – h_{r}R_{L}A_{i}

Finding **Output impedance Z**_{o}

It is ratio of output voltage to output current with V_{s} =0. Then the value of output current becomes

I_{o} = V_{o}h_{o} + h_{f}I_{b}

I_{i} = -h_{r}V_{o}/R_{s} + h_{i}

Z_{o} = V_{o}/I_{o} = 1/[h_{o} – (h_{f} h _{r} /h_{i}+ R_{s})]

The common base configuration hybrid model is also shown below. It is the hybrid equivalent of a CB transistor. As we also know input in common base transistors is applied between base emitter terminals. Then the output is collected from the collector emitter junction. Then value of input voltage V_{be} and output current I_{C} are as

V_{be} =h_{ib} i_{b} +h_{rb} V_{C}

i_{e} = h_{fb}i_{b} + h_{ob}V_{C}

The hybrid expression can also be obtained from the general hybrid formula discussed above by adding a second subscript letter b which commonly stands for base with the h-parameters.

As derived earlier the value of current gain for CB configuration will be

A_{i} = -(h_{fb} / (1+ h_{ob} r_{L})

r_{L}→ AC load resistance.

But r_{L }= R_{c}|| R_{L}

Since h_{fb} is a positive number therefore A_{i} of a CE amplifier is negative.

Then value of resistance at the input terminal in the figure is

R_{i }= h_{ib}+ h_{rb} A_{i }r_{L}= h_{ib }– ((h_{rb}h_{fb })/ (h_{ob} + (1/r_{L})))

The input resistance of the amplifier stage also depends upon the biasing arrangement. Then a fixed biased the stage input resistance is,

R_{is}= R_{i }

A_{v} = A_{i } r_{1 }/R_{i}

We also know that common base amplifiers have positive current gain. Hence, the voltage gain is also positive. Therefore, the output and input are in phase. Then h-parameter is

A_{v} = h_{fb } r_{L }/(h_{ib} + Δh r_{L})

Δh = h_{ib } h_{ob }– h_{rb } h_{fb}

R_{o} = R_{s } + h_{ib }/(R_{s }h_{ob} + Δh)

Δh = h_{ib } h_{ob }– h_{rb } h_{fb}

**Overall Voltage Gain**

A_{vs} = A_{v } R_{is }/(R_{s} + R_{is})

**Overall Current Gain**

A_{is} = A_{vi} R_{s }/(R_{s} + R_{is})

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]]>The post What is Block Diagram of TV Communication? appeared first on Goseeko blog.

]]>The below figure shows the TV broadcast transmitter.

- There are two sections of the transmitter unit.
- One unit is responsible for generation of video signals. This unit receives pictures and based on them it generates the video signals.
- This video signal then helps to modulate the Radio frequency signal. The antenna further transmits this signal.
- The other unit generates an audio signal which contains information in the form of sound. This signal then modulates another RF signal.
- We use only one antenna for both transmission and reception of signals.
- Now there mixing of these two video and audio signals.
- We require an amplifier to amplify these audio and video signals before they could modulate their respective RF carriers.
- The audio and video amplifiers help in amplification.
- We use an AM transmitter for Amplitude Modulation of video signals.
- Whereas we use FM modulators for frequency modulation of sound information.
- The scanning of electron beam from the actual picture through a scanning circuit which produces corresponding video signals.
- At the receiving end also the same process is used.
- Hence, we need synchronizing circuits at both transmitting as well as receiving ends,

- The transmission section of the broadcast unit is has two main sections.
- One which modulates the amplitude (video) and another which modulates frequency (audio).
- For generating RF signal frequency we use Master oscillator. This master oscillator generates sub multiple carriers.
- These carriers then drive frequency multipliers for obtaining the correct value of carriers.
- The Class C tuned amplifiers are harmonic generators.
- A buffer exists between the master oscillator and harmonic generator.
- The carrier of the video transmitter is fed to AM and also to FM in the audio transmitter.
- As the amplification is of low level, linear amplifiers amplify these modulating signals.
- The video and audio signals are separately produced. They are combined and then fed to the transmitting antenna.

- The receiver end produces back the images from the amplified signals received at the receiving antenna.
- The receiver circuit amplifies and converts video and audio RF signals into visual images with their audios.
- The images generated can be colored or black and white.
- To fulfil this purpose the superheterodyne receivers which simultaneously amplifies and converts audio and video RF signals.
- The tuner picks up the required signal and then converts it to a lower frequency.
- This frequency is in between the intermediate frequency pass band.
- An amplitude detector, video amplifier and intermediate frequency amplifier forms a signal processing unit.
- There is a color processing circuit for chrominance signals.
- The control electrodes of the kinescope receive a brightness signal and color difference signals.
- The extraction and decoding of chrominance signals is in color processing circuits.
- The horizontal and vertical scanning circuits form a scanning generator unit.
- For exciting purposes, an electron gun kinescope interface has static and dynamic white balance controls. They also regulate the focusing beam.
- There are different amplifiers for amplifying frequency in the audio section.
- The power supply section will convert the main supply voltage into the supply voltage for the TV set.

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]]>The post What is Minimum Mode Configuration of 8086? appeared first on Goseeko blog.

]]>8086 microprocessor operates in 2 modes :

1. Minimum mode

- It can be selected by setting the MN/MX pin to logic 1 and it acts like a single microprocessor .
- In this mode, all the control signals are provided by the microprocessor chip itself.

2. Maximum mode

- This operation can be selected by setting the MN/MX pin to logic 0 and the microprocessor acts like a multiprocessor.
- It provides the signals for implementing a multi core processor system environment and in this each processor executes its own program.
- In this type of system environment, some system resources that are common to all processors are present.
- They are known as global resources.
- Co processor means there is a second processor in the system, but both of them cannot access the system bus at the same time.
- One processor passes the control of the system bus to the other & then can also suspend its operation.

- It is an 8-bit latch.
- Basically it is a buffered D flip flop.

- This latch separates the multiplexed address received from the data bus by using control signal ALE. This ALE signal is an active high signal.
- This ALE signal is connected to the strobe of the latch.
- We need 3 latches here because the address is 20 bits.

- 8286 is an 8-bit transceiver.
- They are data amplifiers and act as bidirectional buffers.
- This trans receivers separates the multiplexed address received from the address or data bus.
- Since the data bus is 16 bits we require 2 trans receivers.
- This transceiver is connected to signals DT/R’ and DEN’. These signals are enabled using DEN signals.
- DT/R’ controls the direction of data on the control bus and it is also connected to T and DEN’.

- It is a clock generator used to provide clocks.
- There is Input/ output transfer from the bus when signal M/IO’= 1. Also, when the signal M/IO’ = 0 input/output operations are performed.
- The read (RD’) and write (WR’) signals are used to differentiate whether a read bus cycle or write bus cycle is performing.
- When signal WR’=0 it performs write operation and when RD’=0 the microprocessor 8086 performs read operation.
- The signal DEN is also used with RD’. This signal enables the external devices so that they can put data on the bus.
- All these control signals (M/IO’, RD’, WR’) are decoded using a 3:8 decoder. Ic 74138 is a 3:8 decoder.

- These are interrupt signals of an 8086 microprocessor. Whenever there is an interrupt from external devices to 8086 INTR=1.
- When the processor is ready to provide service to external devices then signal INTA’= 0.
- The other devices can make bus requests by sending signal HOLD.
- The 8086 acknowledges them through HLDA signals in return.

The processor cannot get the control of the bus until the master does not set HLDA=0.

The timing diagram of 8086 minimum mode operation is explained below.

- There are four t-states of the bus cycle for microprocessor 8086.
- These T-states are T1,T2,T3 and T4
- During the T1 state the processor gives the address on the bus for 1 T-state.
- In T2 state the processor changes the bus direction.
- In T3 and T4 states the data is transferred.
- The wait signal is also generated between

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]]>The post What is Boolean Algebra? appeared first on Goseeko blog.

]]>Here, the Boolean postulates and basic laws that are used are given underneath.

**Boolean Postulates**

- Considering the binary numbers 0 and 1, Boolean variable (x) and its complement (x’).
- They are known as
**literal**. - The possible
**logical OR**operations are:

x + 0 = x

Also, x + 1 = 1

x + x = x

And x + x’ = 1

- Similarly, the possible
**logical AND**operations are:

x.1 = x

x.0 = 0

x.x = x

x.x’ = 0

We can verify these postulates by simply replacing the Boolean variables with 0 or 1.

The basic laws of Boolean Algebra are:

- Commutative law
- Associative law
- Distributive law

**Commutative Law**

According to this law changing the sequence of the variables does not affect the output.

The logical OR & logical AND operations between x & y are shown below

x + y = y + x

x.y = y.x

The OR operation is represented by ‘+’ and AND operation by ‘.’

This law exists for logical OR and AND operation.

**Associative Law**

This law states that the order of operation does not matter as the result remains unaffected. The equations below make it more clear.

x + (y + z) = (x + y) + z

x.(y.z) = (x.y).z

This law exists for logical OR and AND operation.

**Distributive Law**

Basically this law helps to remove the brackets and solve the logical expression. The brackets can have either AND or OR logic. The distribution of logical OR & logical AND operations between variables x, y & z are :

x.(y + z) = x.y + x.z

x + (y.z) = (x + y).(x + z)

It works good for logical OR and logical AND operations.

The above laws are basic laws and can be verified by substituting the Boolean variable with ‘0’ or ‘1’.

Basic theorems of Boolean Algebra are

- Duality theorem
- De Morgan’s theorem

**Duality Theorem**

As the name says we find the dual of the given Boolean expression. We replace AND operation with OR and vice versa. We replace all zeros by 1. There is always a dual function for every Boolean function.

.

As seen from the above table there are two Boolean equations and are dual to one other.

With the help of the duality theorem we can easily verify the Boolean equations of each group.

**De Morgan’s Theorem**

- De Morgan’s Theorem helps us to find the complement of Boolean functions.
- According to this law the complement of the sum of variable is equal to product of complement of each variable.
- We can understand this law using two variables x and y as

(x + y)’ = x’.y’

- The second way or the dual of the above law with variables x and y is

(x.y)’ = x’ + y’

- The complement of the product of two variables x and y is equal to the sum of complement of each variable.
- This theorem is applicable for more than two variables as well.

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]]>The post What are CE CB CC transistor configurations? appeared first on Goseeko blog.

]]>The notation and symbols of pnp and npn transistors are given below:

- Here the base is common to both the input and output sides of the configuration.
- The flow of holes will govern the direction of current.
- Hence, Ic = Ib + Ie
- Where Ic, Ib, Ie are the collector, base and emitter currents respectively.
- The graphical symbol of the PNP common base configuration is

- The arrow in the above symbol shows the direction of emitter current in the device.
- Now, to study the behavior of the device we require two characteristics:

**Input Characteristic Curve** **of CB**

- It is the relation between the input current I
_{E}to the input voltage V_{BE}for various levels of output voltage V_{CB}. - It is also known as driving point characteristics.

**Output Characteristic Curve** **of CB**

- It is also the relation between the output current I
_{C}to the output voltage V_{CB}for various levels of input current I_{E}. - Also known as the collector set of characteristics.
- Therefore, it has three basic regions:

**Active Region**

- Here, the base-emitter junction is forward biased and collector-base junction is reverse biased.
- Since the input current I
_{E }increases above zero, output current I_{C }increases to a magnitude equal to I_{E}as determined by the basic transistor current relationship. - So, the first approximation determined by the curve is

I_{C} ≈ I_{E}

**Cut-off Region**

- It is defined as the region where the collector current I
_{C}is equal to 0A. - Here, the base-emitter junction and the collector-base junction both are in reverse bias.

**Saturation Region**

- It is the region that lies towards the left of V
_{CB}= 0V. - Since the base-emitter junction and the collector-base junction both are in forward bias.

- The notation and symbols of npn and pnp transistors are given below:

- In the above figure all the currents are shown in their actual conventional directions.
- The current relation developed earlier is still applicable,
- I
_{E}= I_{B }+ I_{C} - Where I
_{E}, I_{B }, I_{C}are the collector, base and emitter currents respectively. - The graphical symbol of the PNP common emitter configuration is

- Now, to study the behavior of the device we require two characteristics:

**Input Characteristic Curve**

- It is the graph between the input current I
_{B}to the input voltage V_{BE}for a range of values of output voltage V_{CE}. - Note that the magnitude I
_{B}of is in micro amperes and that of I_{C}is in milli amperes.

**Output Characteristic Curve**

- It is the graph between the output current I
_{C}to the output voltage V_{CE}for a range of values of input current I_{B}. - The three basic regions are:

**Active Region**

- Here, the base-emitter junction is forward biased and collector base junction is reverse biased.
- These are the same conditions that existed in the active region of the common base configuration.
- This can also be employed for voltage, current or power amplification.

**Cut-off Region**

- Here I
_{C}is not equal to zero when I_{B}is zero. - For linear amplification purposes, it is defined as I
_{C}= I_{CEO}. - The region below I
_{B}= 0µA is to be avoided for undistorted output signals. - When the transistor is used as a switch, the condition should be ideally I
_{C}= 0mA for a chosen V_{CE}voltage.

**Saturation Region**

- It is the region that lies towards the left of V
_{CE}= 0V.

The notation and symbols of npn and pnp transistors are given below:

- In the above figure all the currents are shown in their actual conventional directions.
- It is used for impedance matching purposes as it has high input impedance and low output impedance.
- It can also be designed using common emitter characteristics.
- Then output characteristics of a common collector is the same as that of common emitter configuration for all practical purposes.
- Then output characteristics are a plot between I
_{E}versus V_{CE }for all values of I_{B.} - The input current of the common collector is also the same as that of common emitter configuration.
- Here the region of operation will ensure that maximum ratings are not being exceeded and also output ratings have minimum distortion.

- The characteristics specifying the minimum V
_{CE}that can also be applied without entering the non-linear region is the saturation region. - Then maximum power dissipation is given by,

P = V_{CE}. I_{C}

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]]>The post What is the Superposition Theorem? appeared first on Goseeko blog.

]]>- This is only applicable to circuits with linear elements.
- If two or more than two independent sources (voltage or current) are operating in the circuit then the voltage across any element or current through any element is the sum of current and voltages due to individual sources.

In order to calculate the contribution made by each source in a circuit it is important to replace other sources without affecting the circuit. This theorem helps to solve complex circuits by converting them to Thevenin’s or Norton’s equivalent circuit.

The voltage source which we need to replace in the circuit is short circuited i.e set to zero. Similarly, if we want to replace the current source it should be open circuited i.e. set to zero.

- The sign conventions are important while summing individual contributions from each source present in the circuit. The positive sign is assigned when the contribution from both sources is in the same direction. The negative sign is assigned when the contribution from both sources is in the opposite direction.
- The circuit components should be linear.
- Since power is a non-linear quantity this theorem is not applicable.

- Firstly, we need to select any one of the sources amongst all the sources present in the circuit.
- Secondly, we replace all the other sources in the circuit with their internal impedances.
- Now simplify the given network and calculate the value of current or voltage across the particular element in the network.
- We should repeat the same process for all the other sources as did for the first one.
- Finally, when we have the values against all the individual sources we sum up all the values of voltages and currents through the circuit element.

Question 1. Find the current trough 3Ω resistance.

Solution:

Firstly, we Short circuit 2V voltage source.

I_{1 }= 0

Secondly, we Open circuit 6A. Then the value of current through 3Ω is

I_{2 }= ⅔ A

Since two voltage sources with different magnitudes in parallel and we cannot connect them as in a single branch, two different currents are not possible (if 5V then I = zero).

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]]>The post What is Norton’s Theorem? appeared first on Goseeko blog.

]]>The short circuit current is then given as

I_{sc} = V_{th}/R_{th}

Norton’s equivalent is obtained by source conversion of Thevenin’s equivalent circuit.

**For network A:**

1. Network A should contain linear elements.

2. Network A can have independent and dependent current and voltage sources.

3. If network A has a dependent source then the controlling parameter must lie in network A itself.

4. Network A should not have any source coupling and magnetic coupling.

**o**** ****For network B:**

1**.**** **It can have linear and non-linear elements.

2. It can have dependent and independent voltage and current sources.

3. It should not have any source and magnetic coupling with network A.

** ****Method for finding R**_{th}**:**

Firstly, open circuit terminal A and B.

1. If the network is operating with only independent sources:

a. Make all sources zero in network A.

b. Find out the equivalent resistance across terminals A and B.

2. If network A is operating with independent and dependent sources:

a. Make all independent sources zero in network A.

b. Connect a generation between A and B.

3. If the network is operating with only dependent sources:

Connect generation between A and B

**Method for V**_{th}**:**

First, open circuit terminal A and B.

Find out the voltage between A and B this is V_{th}

**Method for I**_{sc}**:**

1. I_{sc} =V_{th}/R_{th}

2. Remove network B and S.C. the terminal A and B and current from terminal A to B I_{sc}.

**Question: Find V _{th} and R_{th} for the circuit shown below?**

Solution

**Finding the Thevenin’s Resistance R**_{th}** **

The **R**** _{th }**is calculated from the terminal a and b. For that we remove all the sources present in the bilateral network. The voltage source is shorted. The circuit after changes is

Then the value of Resistance R_{th} is

The value of voltage **V**_{th}** **is

**Finding I**_{sc}** from circuit directly:**

Applying KCL to the above circuit we get

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]]>The post What is the Concept of data communication on GPRS? appeared first on Goseeko blog.

]]>The GSM network is used more efficiently in the present GPRS systems. The concept of this system is to build a packet based mobile network. The present network not only provides an interface for handling data but also has protocols.

- There is a need for software upgrade and installation of Packet control units for each BSC.
- For the BSS this PCU provides physical and logical data interference for packet data traffic.
- The BTS does not require hardware enhancement but needs software upgrade.
- When there is data traffic from the subscriber’s phone, it is sent to BTS through the air interface.
- Later on to BSC as normally in GSM call.
- At the output side both voice and data traffic are separated.
- Voice is sent to MSC as in GSM and data to SGSN via PCU.

The node has Gateway GPRS Support Nodes (GSNs) and, Serving GPRS Support Node (SGSN)

Gateway General Packet Radio Service. Support Node (GGSN)

It behaves as a router or an interface between the external networks. It not only has the routing information but also tunnels packers through IP based internal backbone. GGSN acts as a packet filter for incoming traffic. For use of external data networks it also collects charging information.

Serving General Packet Radio Service. Support Node (SGSN)

The main purpose of SGSN is

- To authenticate General Packet Radio Service mobiles.
- Registration of mobiles.
- Mobility management.
- To check information on charging so that it can be used in air interface.

Internal Backbone

This is an IP based network which carries packets between GSNs. The internal backbone does not require any information about the domain which is outside the GPRS network as it uses tunneling. SS7 signaling is also used from GSN to MSC and HLR.

Routing Area

The Routing area concept is explained well in General Packet Radio Service. This is quite similar to the location area of GSM. The small difference is the routing area has few cells compared to the location area. Hence it requires less radio resources for broadcasting a page message.

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]]>The post How to design a Synchronous counter? appeared first on Goseeko blog.

]]>The basic design steps for these counters are discussed in detail.

- First we find the number of flip flops required for the design of a synchronous counter.
- The number of flip flops can be determined from 2^n ≥ N.

Where: N →number of states and n →number of flip flops.

- Next ew select the flip flop for the design.
- Then we draw the state diagram of that counter.
- With the help of an excitation table of flip flops we determine the excitation table of the counter.
- At last we simplify the excitation table using K-map.

The design of the mod-N synchronous counter is done through following steps.

**Step 1 :** **Find number of flip flops **

For the mod N counter we can find the number of flip flops from relation

**N <= 2n**

Let us consider N= 10. So,

**For n =3, **10<=8, which is not true. Hence again considering n= 4

** **10<=16

This holds true.

Therefore the number of flip flops required is 4 for the Mod-10 counter.

**Step 2 : Excitation table of Flip flops **

We chose a T flip flop for the design. Then the excitation table for T flip flop is as shown

**Step 3 : State diagram andCircuit excitation table **

The mod-10 counter counts ten states from 0 to 9. This counter is also called the decade counter. We use four flip flops here. They are reset When QD QC QB QA = 1001.

**Circuit excitation table **

Now QD QC QB QA are the present states of flip-flops and Q*D Q*C Q*B Q*A is the next counting state of these Flip flops.

When there is transition in the present of QD the value changes from 0 to 1 or vice versa.

**Step 4 : Simplify K-map for each FF input in terms of flip-flop outputs as the input variable **

**Step 5 :Circuit diagram **

The negative edge trigger is used for toggle.

- The clock pulse is synchronous to all flip flops.
- Then the input to every flip flop is as per the equation of K map.

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]]>